1. Field of the Invention
The present invention relates generally to a spiral inductor serving as an inductance element spirally formed on a substrate, and a method for fabricating a semiconductor integrated circuit device having the same.
2. Related Background Art
As one of inductance function elements provided in a semiconductor integrated circuit device (which will be simply hereinafter referred to as an IC), there is a so-called plane spiral inductor. This is designed to obtain a required inductance with such a structure that a plane spiral wiring is formed on a substrate.
However, if a plane spiral inductor is actually formed on a substrate, there is a problem in that it is not possible to sufficiently suppress a coupling between the spiral wiring and the substrate, so that part of high-frequency energy escapes into the substrate, thereby lowering characteristics (Q-value) of the inductor.
Referring to the accompanying drawings, this problem will be described below in detail. Furthermore, the same reference numbers are given to the dame portion in the following drawings, and the descriptions thereof will be suitably omitted.
FIG. 19 is a plan view showing an example of a conventional spiral inductor, and FIG. 20 is a sectional view of the spiral inductor taken along line A—A of FIG. 19.
A spiral inductor 100 shown in FIGS. 19 and 20 comprises: a substrate 1 having a dummy element 2, which will be described later, on its surface; an extracting wiring 5 which is formed on the substrate 1 via insulating films 3 and 4; a second layer wiring 7 which is formed on the substrate 1 via the extracting wiring 5 and an insulating film 6; and a protective film 9 which is formed so as to cover the second layer wiring 7. The extracting wiring 5 is formed in line by patterning using a photoresist. The second layer wiring 7 is formed so as to have a plane spiral shape by patterning using a photoresist. Of both end portions of the extracting wiring 5, an end portion on the center side of the spiral inductor 100 is connected to an end portion of the second layer wiring 7 on the center side of the spiral, and an end portion of the extracting wiring 5 on the peripheral side of the spiral inductor 100 is connected to a circuit element (not shown) in an IC. The spiral outermost end portion of the second layer wiring 7 is also connected to another circuit element (not shown) in the IC. Thus, a high-frequency circuit is formed.
In the surface of the substrate 1, an element isolating shallow groove is formed so that the remaining portions are protruding portions arranged in the form of islands. The top faces of these protruding portions form Si regions 2 about a few micrometers square. These Si regions 2 are called dummy elements. The shallow groove is filled with the insulating film 3, so that an STI (Shallow Trench Insulator) structure is formed. The reason why such dummy elements 2 are provided in the surface of the substrate is as follows.
The above described element isolation based on the STI is the mainstream element isolating system at present. In this STI isolating process, after the insulating film 3 filled in the element isolating groove, planarization is carried out by the chemical and mechanical polishing (which will be simply hereinafter referred to as CMP) technique. However, in this planarization process, if a wide field region (of about one hundred μm or more) exists on the surface of the substrate, a phenomenon called dishing that only the region is scraped off is caused. In order to solve such a problem in the planarization process, a method for arranging dummy elements in the form of islands is adopted. In particular, when a relatively large inductance, e.g., an inductance of a few nH, is required, the size of the spiral inductor is a few hundreds μm square, so that it is necessary to arrange dummy elements to prevent dishing.
However, if the dummy elements are provided, there are two new problems as follows.
First, as shown in FIG. 20, the distance between the dummy element 2 and the inductor wiring portions 5, 7 is shortened by a difference in level of the protruding portion, so that there is a problem in that part of high-frequency energy particularly passes through the dummy element 2 directly below the wiring to leak into the substrate 1.
Second, in recent semiconductor fabricating processes, the surface of Si is generally silicidated in order to enhance the performance of an active element. At this time, the surface of the dummy element 2 in the lower portion of the inductor is also silicidated. This means that a layer having a very low resistance is formed directly below the inductor, so that there is a problem in that characteristics (Q-value) of the inductor deteriorate.